1. Field of the Invention
The present invention relates to an image signal repeater apparatus which receives an image signal having a predetermined format which is used by a personal computer (hereafter referred as a PC), from an image signal generator such as a PC, and then recovers the image signal in the predetermined format and outputs this. The present invention also relates to an image display apparatus with an image signal repeater function which in addition to having the function of this image signal repeater apparatus, is for displaying the received signal on a display device, for example an LCD, CRT, plasma display or electroluminescent display, and to a method of controlling the image signal repeater apparatus and the image display apparatus.
2. Background Art
FIG. 1 shows an image display system commonly used to transmit an image signal over long distances. In FIG. 1, this image display system comprises; an image signal generator 11, an image signal generating device 12 contained in the image signal generator 11, and also comprises either one or a plurality of image signal repeater apparatuses 13 and image display apparatuses 14.
In the diagram the image signal generator 11 has an internal image signal generating device 12, and outputs an image signal created by the image signal generator. The output image signal is relayed by the image signal repeater apparatuses 13, and displayed on the image display apparatus 14.
FIG. 11 is a block diagram showing the internal construction of a conventional image signal repeater apparatus 13 used in the image display system described above. In FIG. 11, this image signal repeater apparatus 13 comprises a receiving terminal 111, an image signal receiving device 112, a clock regeneration device 115 contained inside the image signal receiving device 112, an image signal transmission device 113, and an image signal output terminal 114.
The operation of the image signal repeater apparatus 13 shown in FIG. 11 is described below with reference to FIG. 1 and FIG. 11. As shown in FIG. 1, the image signal output from the image signal generator 11 is input to the image signal repeater apparatus 13. As shown in FIG. 11, the image signal input to the image signal repeater apparatus 13 is input to the image signal receiving device 112 via an input connector 111.
To enable the image signal receiving device 112 to reliably recover the received image signal, such a device generally comprises a clock regeneration device 115 incorporating a phase lock loop (hereafter referred to as a PLL). The image signal receiving device 112 receives the image signal reliably according to the clock recovered by the clock regeneration device, and outputs the recovered image signal to the image signal transmission device 113. The image signal transmission device 113 then outputs the image signal received from the image signal receiving device 112, in a predetermined format. As shown in FIG. 1, it is possible to transmit the image signal over longer distances by connecting image signal repeater apparatuses 13 in multiple stages.
Furthermore, FIG. 12 is a block diagram showing the section of the repeater apparatus proposed in Japanese Unexamined Patent Application, First Publication No. Hei 10-51358 (patent document 1) which is responsible for repeating the image signal. In FIG. 12, this image signal repeater apparatus 13 comprises a receiving terminal 121, a demodulation section 122, an image memory 123, a modulation section 124, a clock generation section 125, and an output terminal 126.
Next, the operation of the image signal repeater apparatus 13 shown in FIG. 12 is described with reference to FIG. 1 and FIG. 12. The image signal generating device 12 shown in FIG. 1 generates an analog signal which is modulated to aid transmission, and outputs the signal as output from the image signal generator 11. As shown in FIG. 12, the output image signal is input to the demodulation section 122, demodulated, and written to the image memory 123.
The image data written to the image memory 123 is read out in synchronization with the clock generated by the clock generation section 125, and output to the modulation section 124. The modulation section 124 then modulates the received image signal in synchronization with the clock generated by the clock generation section 125, and outputs the signal.
Next, several examples of other related background art are described in brief. An example of a conventional repeater apparatus is a receiver apparatus used to recover an unstable signal component such as a television signal, wherein the sampling clock is determined based on several calculations (see patent document 2, for example). Another example is a repeater apparatus in which a transmission signal is received and recovered by a PLL which operates at a clock set to N times the transmit clock, and is then recovered by a PLL which operates at a clock set to M times that of the transmit clock (where N<M and M, N are natural numbers) and then transmitted (see patent document 3, for example).
Furthermore, there are transmitter-receivers which perform data transmission over an ATM (Asynchronous Transfer Mode) network by using a timestamp for correction based on the network clock, thus ensuring the corrected recovered clock is generated (patent document 4, for example). Furthermore, another example of conventional technology is an apparatus which instead of using a PLL, temporarily stores data received via the transmission path in a buffer, and keeps the average rate of data transmission constant by switching the speed of the read clock (see patent document 5, for example).
Furthermore, various constructions are proposed for synchronizing conventional clock generations circuits with an input signal, for the purpose of improving performance and the like (see patent documents 6 to 8, for example).
[Patent Document 1]
Japanese Unexamined Patent Application, First Publication No. Hei 10-51358 (pages 3 to 4, FIG. 1)
[Patent Document 2]
Japanese Unexamined Patent Application, First Publication No. Hei 6-338880 (pages 3 to 4, FIG. 1)
[Patent Document 3]
Japanese Unexamined Patent Application, First Publication No. Hei 7-131492 (page 2, FIG. 1)
[Patent Document 4]
Japanese Unexamined Patent Application, First Publication No. Hei 11-355280 (page 5, FIG. 1)
[Patent Document 5]
Japanese Unexamined Patent Application, First Publication No. Hei 10-327158 (page 3, FIG. 1)
[Patent Document 6]
Japanese Unexamined Patent Application, First Publication No. 2002-217715 (page 4, FIG. 2)
[Patent Document 7]
Japanese Unexamined Patent Application, First Publication No. Hei 8-191294 (pages 5 to 6, FIG. 5)
[Patent Document 8]
Japanese Unexamined Patent Application, First Publication No. Hei 10-285150 (pages 8 to 9. FIG. 1)
An image signal repeater apparatus 13 such as that shown in FIG. 11 does not include a function for reducing distortion in the time direction, contained in the clock of the received image signal (referred to as jitter below), and may even cause jitter internally because of the noise within the apparatus. When image signal repeater apparatuses 13 are connected in multiple stages as shown in FIG. 1, the jitter in the clock accumulates and increases with the increase in stages.
Furthermore, the clock regeneration device 115 shown in FIG. 11 typically uses a PLL for clock regeneration, but when the PLL is used there is a limit to the phase range which can be locked, and therefore the phase cannot be locked properly once the jitter exceeds a certain amount.
In the conventional construction shown in FIG. 12, since a clock which is not synchronized with the input signal is used in reading from memory and in signal modulation, jitter does not accumulate when apparatuses are connected in multiple stages. Hence, the above problem does not occur. However, since the internally generated clock is fixed at a certain value, regardless of the clock of the received signal, such an apparatus cannot receive image signals that can have a variety of frequencies, such as signals output by a PC. Furthermore, since an analog method is adopted for signal modulation and demodulation, then with multistage connection, modulation errors are commonplace, making it increasingly difficult to reliably recover the original signal as the number of stages increases.
Furthermore, with the sampling clock regeneration method described in patent document 2, the sampling clock is determined based on multiple calculations. Therefore there is a problem in that high speed signal determination is difficult, and the circuitry and configuration is complicated.
Moreover, in the multi-stage relay system described in patent document 3, if jitter is present in the input signal, a problem occurs in that the PLL itself follows the jitter, failing to reduce the jitter sufficiently. Furthermore, since the PLL is operating constantly, if the transmission signal is an image signal composed of multiple frames, the effect of jitter is also apparent within the image period.
Furthermore, in the data transmission system shown in patent document 4, since a clock called a network clock, which is separate from the internally generated clock, is used, specific architecture is required for that purpose.
Moreover, in the clock generation apparatus shown in patent document 5, the internally generated clock is not switched according to the original clock of the input signal, and is instead switched according to the amount of buffered data. Consequently, it is difficult to perform control in which frequency switching is performed in accordance with a specific signal, for example it is difficult to accurately control the generation of a synchronization signal corresponding to an image signal composed of multiple frames.